1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
A manufacturing process of a semiconductor device is broadly divided into a step of partitioning a semiconductor wafer into a plurality of element regions by a lattice-shaped dicing line and forming an integrated circuit in each of element regions, a step of cutting the semiconductor wafer along the dicing line to section the respective element regions as semiconductor elements (semiconductor chips), and a step of mounting the semiconductor element on a wiring substrate and packaging it.
To cope with the miniaturization and speeding up of the semiconductor element, the application of low dielectric constant insulating film (Low-k film) which is effective in suppressing a wiring delay (RC delay) (suppression of delay especially by reduction in parasitic capacitance C of wiring) to semiconductor element is promoted. As constituent materials of the Low-k film, for example, fluorine-doped silicon oxide (SiOF), carbon-doped silicon oxide (SiOC), organic silica, porous bodies of them and the like are used.
To a cutting step of a semiconductor wafer, blade dicing which cuts the semiconductor wafer by mechanically cutting it by using a diamond blade is generally applied. When the semiconductor wafer using a Low-k film is cut by blade dicing, there is the problem of easily causing film peeling, cracks and the like due to brittleness and low adhesion strength of the Low-k film. Therefore, prior to blade dicing of the semiconductor wafer having the Low-k film, it is proposed to irradiate laser beam along the dicing line partitioning respective element regions to cut the Low-k film (see JP-A2005-252196 (KOKAI), and JP-A 2006-108489 (KOKAI)).
Concerning the mounting structure (package structure) of the semiconductor element, an FC-BGA (Flip Chip-Ball Grid Alley) package having flip-chip connection in which a wiring path of the semiconductor element and the substrate is short in order to exhibit the performance of the semiconductor element sufficiently is known. In FC-BGA package, the structure in which a heat sink is bonded on the semiconductor element is applied, in order to enhance heat release performance from the semiconductor element which is connected on the wiring substrate. A lid for sealing the semiconductor element is allowed to have the function as the heat sink, and this is bonded to the back surface of the semiconductor element.
The lid which is also used as the heat sink is generally composed of a metal material from the viewpoint of heat release performance. When the package structure including the lid is applied to the semiconductor element having the Low-k film, film peeling in a thermal cycle test (TCT) which is an environment life test becomes a problem. Thermal stress at the time of TCT gives tremendous stress to an edge portion (chip edge) of the semiconductor element existing between the substrate and the lid (heat sink), and this causes film peeling from the chip edge. Because the Low-k film has low film strength of itself and low adhesion to other films, there is the problem of easily causing film peeling on TCT.
Concerning film peeling by a machining damage to the Low-k film at the time of dicing, the film peeling is suppressed by reducing a mechanical damage by applying laser machining. However, film peeling due to the Low-k film also occurs by addition of stress to the chip edge based on the package structure, in addition to the mechanical damage at the time of dicing. Film peeling of the Low-k film based on the package structure cannot be sufficiently suppressed by only the preventive measures against film peeling by application of laser machining. Therefore, in order to enhance manufacturing yield and reliability as the final semiconductor package, suppression of film peeling of the Low-k film based on the package structure is required.